1. Field of the Invention
The present invention relates to flash memory, and more particularly to flash memory devices which use stacked memory die and the Serial Peripheral Interface (“SPI”).
2. Description of Related Art
Serial flash memory has become a popular alternative to conventional parallel flash memory. Serial flash memory provides many advantages, including small footprint packaging, low pin-count, simplified printed circuit board layout, low power consumption, performance comparable to parallel flash memory, and reduced device and system-level costs. The Serial Peripheral Interface (“SPI”) is widely used in serial flash memory, and devices which are configurable for single-bit SPI or multi-bit SPI, including multi-bit instruction and/or address input and multi-bit data output, have become particularly popular. The SPI interface has many advantages. Single-bit SPI allows for broad compatibility, while multi-bit SPI when combined with certain types of flash memory and high clock speeds allows for fast “code shadowing to RAM” and “execute in place” (“XIP”) code storage applications. Additional information on single-bit and multi-bit SPI may be found in, for example, U.S. Pat. No. 7,558,900 issued Jul. 7, 2009 to Jigour et al., and in various publications by Winbond Electronics Corporation, including Winbond Electronics Corporation, W25Q256FV: spiflash 3V 256M-Bit Serial Flash Memory with Dual/Quad SPI & QPI, Revision F, Hsinchu, Taiwan, R.O.C., Oct. 16, 2013; and Winbond Electronics Corporation, W25N01 GV: spiflash 3V 1 G-Bit Serial SLC NAND Flash Memory with Dual/Quad SPI & Continuous Read, Preliminary—Revision B, Hsinchu, Taiwan, R.O.C., Nov. 26, 2013.
Serial flash memories typically are offered in densities from 512 Kilobit to 1 Gigabit. However, the demand for higher density serial flash devices at lower per-bit cost keeps increasing. Monolithic silicon die at high density is feasible but costly. Stacking of lower density die of the same type to form a high density serial flash memory device is an alternative. With a density of 256 Mb for a single die, for example, two serial flash memory die of the same type have been stacked to achieve a 512 Mb (2×256 Mb) device, and four serial flash memory die of the same type have been stacked to achieve a 1 Gb (4×256 Mb) device.
Moreover, flash memory die of different types has been stacked to achieve a single memory device having different characteristics. Flash memory typically is NOR-type or NAND-type. In NOR-type flash memory, each memory cell is connected between a bit line and ground. The typical characteristics of NOR flash are low density, high read speed, slow write speed, slow erase speed, and random access. Since NOR flash has fast random-access memory read, microprocessors generally can use NOR flash memory for fast “code shadowing to RAM” and “execute in place” applications. In NAND-type flash memory, a number of memory cells are connected in series between a bit line and ground. The typical characteristics of NAND flash are high density, medium read speed, high page write speed, high erase speed, and an indirect or I/O like access. NAND-type flash memory is particularly well suited to systems requiring high-capacity data storage because of its high speed sequential writing capability and high density at low cost. Some types of NAND-type flash memory have been modified to provide sufficient SPI-NOR like performance in code shadowing applications. Further information on the stacking of NOR die and NAND die, and the stacking of a performance-enhanced NAND die and a NAND die, are described in United States Patent Application Publication No. US 2012/0084491 published Apr. 5, 2012, in the name of Eungjoon Park et al.
The techniques to operate a flash memory device having stacked SPI flash memory die are not entirely satisfactory. In one stacking approach disclosed in Spansion Inc., Data Sheet, S70FL256P 256-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI Multi I/O Bus, Revision 05, Jan. 30, 2013, two identical 128 Mb dies are stacked with their individual /CS inputs bonded to respective pins of the package to form the flash memory device. Disadvantageously, the controller is required to provide and manage multiple /CS control signals. Moreover, the dedication of two pins of an 8-pin package for chip select precludes one of the pins needed for the Quad SPI interface, thereby eliminating Quad SPI in an 8-pin package.
In another stacking approach disclosed in Micron Technology Inc., N25Q512A 1.8V, Multiple I/O Serial Flash Memory, September 2013, two dissimilar die are stacked and from a user standpoint behave as a monolithic device, except with regard to READ MEMORY and ERASE operations and status polling. While such a device can operate with a Quad I/O SPI protocol in an 8-pin package, the manufacturing costs tend to be greater due to the complexity of the special design.